In a semiconductor integrated circuit, a power-supply control circuit performs a power-saving control of a circuit block. A conventional power-supply control circuit controls a power-supply voltage, a reset signal and a clock signal supplied to the circuit block, in accordance with a power-down request signal, a wake-up request signal and a clock signal, supplied from the circuit block and other circuits within the LSI. The power-supply control circuit includes a controller (control unit), a transistor, a counter and an OR gate (logical sum gate).
The control unit is a state machine which determines the state of a power-down signal a start signal and a stop signal to be outputted therefrom, in response to the state and timing of the clock signal, the power-down request signal and the wake-up request signal supplied thereto. The transistor controls on/off state of the power-supply voltage supplied to the circuit block in response to the power-down signal, supplied from the control unit. The counter counts the clock signal in response to the start signal, supplied from the control unit. The counter cancels the reset signal to the circuit block when the count value reaches a predetermined value. The OR gate provides a control of the clock signal to be supplied to the circuit block, in accordance with the stop signal supplied from the control unit.
In such an LSI, when the power-down request signal turns from high to low, the stop signal supplied from the control unit turns to high. This allows the clock signal, outputted from the OR gate, to keep being high in level, and stop to be supplied to the circuit block.
When several clocks are generated after the stop signal turns to high, the power-down signal, outputted from the control unit, turns from low to high in level. The transistor turns off and no power-supply voltage is supplied to the circuit block. As a result, the circuit block turns in the power-down state.
After that, when a request for operation is provided to the circuit block, the wake-up signal, outputted from another circuit within the LSI, turns low to high in level. The power-down signal and stop signal, both outputted from the control unit, turn to low. The start signal keeps being high in level for a predetermined period of time, and then turns to low.
When the power-down signal turns to “L”, the transistor turns on. The power supply voltage starts being supplied to the circuit block and gradually increases in level. When the stop signal turns to “L”, the clock signal starts being supplied to the circuit block.
On the other hand, when the start signal keeps being high for a predetermined period of time, the counter is reset, allowing the reset signal turns to low “L”. As a result, the circuit block turns into a reset mode. When the start signal returns to low “L” after a predetermined period of time, the counter starts counting the clock signal. Then, when the count value of the counter reaches a predetermined value, the reset signal supplied to the circuit block turns to high “H”. As a result, the reset state (reset mode) is cancelled, allowing the circuit block to start its operation.
The reset mode of the circuit block is cancelled after a predetermined period of time since the power-supply voltage starts being supplied to the circuit block, so that the circuit block operates in a wake-up mode reliably.
However, according to the above-described conventional LSI, the time, taken to stabilize the power-supply voltage in the wake-up mode, is dependent on a fixed value of the counter. This fixed value defines the time taken to securely stabilize the power-supply voltage in view of variations in the characteristics of the circuit block. Accordingly, the fixed value is a value allowing for an excessive margin for the actual time required to reach the voltage capable of the circuit operation. This made difficult a prompt resumption of the circuit operation after receipt of the wake-up request signal.